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Graphene modelocked VECSELs C.A. Zaugg1*, V.J. Wittwer2, Z. Sun2, ...
www-g.eng.cam.ac.uk/nms/publications/pdf/896607.pdf14 Mar 2014: We use a 10 cm cavity at 1.5 GHz, with various OC transmission rates and gain chips to fully test our GSAMs. -
1.1 Gigahertz Multi-Transistor Graphene Integrated Circuits
www-g.eng.cam.ac.uk/nms/publications/pdf/06724538.pdf4 Feb 2014: ROs are the standard test-beds for evaluating ultimate performance limits and the highest possible clock rates of digital logic families (58).
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